In integrated circuit design, great emphasis is placed on the operating speed of a circuit. For high-speed applications, emitter coupled logic (ECL) technology is often used because of its speed advantage over transistor-transistor logic (TTL) technology.
In its simplest form, an ECL gate comprises a differential pair of NPN transistors, the first transistor having its base connected to an input and the second transistor having its base connected to a reference voltage. If the input voltage is greater than the reference voltage, the collector voltage of the first transistor decreases and the collector voltage of the second transistor increases. If the input voltage is less than the reference voltage, the collector voltage of the first transistor increases and the voltage at the collector of the second transistor decreases. Hence, the voltage on the collector of the second transistor follows the voltage of the input signal and the voltage at the collector of the first transistor follows the complement of the input signal.
The common emitter differential pair, while faster than TTL logic, is still slower than other transistor structures, such as emitter followers. In fact, emitter followers are often connected to the collectors of the differential pair to allow the circuit to drive a larger load. Typically, the addition of emitter follower transistors will add a delay of about 20-30% to the circuit.
Circuitry for increasing the output transition speed of the complement output in response to a low-to-high transition of the input is described in U.S. patent application Ser. No. 302,063, entitled "Active Load for ECL Type Outputs", to Ovens, filed on Jan. 24, 1989, which is incorporated by reference herein. In designing a circuit, however, the worst case specifications must be considered; therefore, to increase the operating speed of the ECL gate, the output transistor speed of the "true" output of the ECL gate must also be increased.
Therefore, a need has arisen to provide a circuit for providing a fast output transition of the true output in response to a low-to-high transition of the input signal.